1. Field of the Invention
The present invention generally relates to voltage generating circuits, and more specifically to improvement of a voltage generating circuit formed in a semiconductor substrate. The present invention has particular applicability to a dynamic random access memory (DRAM).
2. Description of the Background Art
Recently, a power supply voltage level has been lowered under demands for high integration and reduced power consumption of a semiconductor device. Provision of a lower power supply voltage to a semiconductor device enables insulating films of a MOS transistor, a MOS capacitor and the like to be thinner, that leads to improvement of the integration and power consumption thereof.
The provision of a lower power supply voltage to a semiconductor device, however, brings about bad results to several voltage generating circuit provided in the semiconductor device. More specifically, a semiconductor device is generally provided with a substrate bias voltage generating circuit for biasing a semiconductor substrate to a prescribed polarity. Since the substrate bias voltage generating circuit is constituted by a charge pump circuit, loss in the bias voltage level can not be ignored if a power supply voltage is reduced. (This problem will be described later in detail.) Similarly, since a boosted voltage generating circuit provided in the semiconductor device is also constituted by a charge pump circuit, loss in a boosted voltage level can not be ignored if the power supply voltage is reduced.
Although the present invention is generally applicable to a voltage generating circuit provided in a semiconductor device, a case in which the present invention is applied to a dynamic random access memory (hereinafter referred to as a DRAM) will hereinafter be described.
FIG. 8 is a block diagram of a DRAM to which the present invention can be applied. Referring to FIG. 8, a DRAM 100 comprises a memory cell array 85 including a multiplicity of memory cells, an address buffer 81 receiving externally applied address signals A0 to An, a row decoder 82 and a column decoder 83 for designating respectively a row and a column of the memory cell array 85 in response to the received address signal, and a sense amplifier 84 for amplifying a data signal read out from the memory cell. Input data Di is applied through a data-in buffer 86. Output data Do is provided through a data-out buffer 87. The DRAM 100 comprises a clock generator 88 generating a clock signal for controlling various circuits provided therein.
The DRAM 100 further comprises a substrate bias voltage generating circuit (shown as "V.sub.BB generating circuits" in the figure) 89 for generating the aforementioned substrate bias voltage V.sub.BB. The substrate bias voltage generating circuit 89 receives a clock signal generated from a ring oscillator not shown, and after being supplied with a power supply voltage Vcc, is continuously driven by the applied clock signal.
A boosted voltage generating circuit 93 is driven by an externally applied row address strobe signal/RAS. More specifically, an RAS input buffer 92 receives the externally applied signal/RAS to apply the received signal to the clock generator 88 and the boosted voltage generating circuit 93. The circuit 93 is driven by the applied signal, and generates a boosted voltage Vpp.
The DRAM 100 further comprises a boosted voltage generating circuit 96 supplying a boosted voltage Vpp to a word line (not shown) through the row decoder 82. The boosted voltage generating circuit 96 also receives a clock signal from the ring oscillator, not shown, to generate the boosted voltage Vpp. The boosted voltage Vpp is applied to a selected word line through the row decoder 82.
Each of the substrate bias voltage generating circuits 89, 93 and 95 and the boosted voltage generating circuit 96 shown in FIG. 8 comprises a charge pump circuit, and generates a desired voltage in response to an applied clock signal. The substrate bias voltage generating circuit has the following circuit structure, for example.
FIG. 6 is a schematic diagram of a substrate bias voltage generating circuit showing the background of the present invention. Referring to FIG. 6, a substrate bias voltage generating circuit 24 comprises inverters 1 and 2, PMOS capacitors 3 and 4, and PMOS transistors 5, 6 and 7. The inverters 1 and 2 respond to a clock signal .phi.0 to provide complimentary clock signals .phi.1 and .phi.2. Each of the PMOS transistors 5, 6 and 7 is assumed to have a threshold voltage Vthp.
FIG. 7 is a timing chart showing the operation of the substrate bias voltage generating circuit 24 shown in FIG. 6. Referring to FIGS. 6 and 7, the operation of the substrate bias voltage generating circuit 24 will be described.
At a time t1, the output signal .phi.1 of the inverter 1 rises from a ground potential (hereinafter referred to as a GND level) to a power supply voltage level (hereinafter referred to as a Vcc level). Here, the GND level corresponds to 0 volt. Although a gate voltage 6g of the transistor 6 tends to rise to the Vcc level because of the coupling of capacitor 4, it actually attains the voltage level Vthp, since the transistor 5 is rendered conductive. At the same time t1, the output signal .phi.2 of the inverter 2 falls from the Vcc level to the GND level, whereby gate and drain voltages of the transistor 7 are lowered because of the coupling of the capacitor 3, causing the transistor 7 to become conductive. The conduction of the transistor 7 causes charges of the substrate to be extracted through the transistor 7, and the extracted charges are held by the capacitor 3. The transistor 6 is turned off in response to the applied gate voltage Vthp.
At a time t2, the output signal .phi.1 of the inverter 1 falls from the Vcc level to the GND level. The gate voltage 6g of the transistor 6 attains Vthp--Vcc because of the coupling of the capacitor 4, and the transistor 6 is turned on. The extracted charges, the charges held by the capacitor 3, are led to the ground through the transistor 6. At this time, the transistor 7 is turned off by the rise of the gate and drain voltages, preventing the extracted charges from flowing back.
As described above, by the input clock signal .phi.0 rising and falling repeatedly, charges are extracted from the substrate, and finally the substrate potential V.sub.BB attains a level -Vcc+Vthp as shown in FIG. 7.
Since the substrate bias voltage generating circuit 24 shown in FIG. 6 employs the transistor 7 having a gate and a drain commonly connected, the substrate potential V.sub.BB can not be lowered below the level -Vcc+Vthp, in principle. As has already been described, the loss for the voltage Vthp by the transistor 7, that is, the rise of i0 the substrate potential V.sub.BB for Vthp, is not preferable, in the light of a recent tendency for the level of the power supply voltage Vcc applied to a semiconductor device to be lowered. Since the level of the power supply voltage V.sub.BB is -VCC+Vthp, the output voltage level rises proportional to the fall of the level of the power supply voltage Vcc. In other words, as the power supply voltage level falls, the loss of the power supply voltage Vthp in the output voltage level can not become made light of.